The 74HC155 is a high speed CMOS dual 2-to-4 line
decoder fabricated with silicon gate C2MOS technology.
It achieves the high speed operation similar to equivalent
LSTTL while maintaining the CMOS low power dissipation. It features dual 1-to-4 line demultiplexers with individual strobe input (1G and 2G), individual data inputs (1C and 2C) and common binary address inputs (A and B). When the decoders are enabled by the strobes, the inverted output of 1C data and non-inverted output of 2C data will be brought to the selected output pins of each section. A 1-to-8 line demultiplexer can be easily built up by providing a data signal to both the 1C and 2C inputs; the output order will be 1Y3 (MSB), 1Y2, 1Y1, 1Y0, 2Y3, 2Y2, 2Y1, 2Y0 (LSB). This device can be used as a 2-to-4 line decoder or a 3-to-8 line decoder when 1C is held high and 2C is held low. All inputs are equipped with protection circuits against static discharge or transient excess voltage.
High speed: tpd = 12 ns (typ.) at VCC = 5 V
Low power dissipation: ICC = 4 μA (max) at Ta = 25°C
High noise immunity: VNIH = VNIL = 28% VCC (min)
Output drive capability: 10 LSTTL loads
Symmetrical output impedance: |IOH| = IOL = 4 mA (min)
Balanced propagation delays: tpLH ~ tpHL
Wide operating voltage range: VCC (opr) = 2 to 6 V
Pin and function compatible with 74LS155
16 pin DIP. Actual brand may vary from picture.