This monolithic, positive-edge-triggered flip-flop utilizes TTL circuitry to implement D-type flip-flop logic with a direct clear (CLR) input. Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output. The 74F174 is characterized for operation from 0°C to 70°C.
Contains Six Flip-Flops With Single-Rail Outputs
Buffered Clock and Direct Clear Inputs
Fully Buffered Outputs for Maximum Isolation From External Disturbances
SOIC 16 package. Actual brand may vary from picture.