These devices contain two independent positive-edge-triggered D-type flip-flops. A low
level at the preset (PRE) or clear (CLR) inputs sets
or resets the outputs regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of
CLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. The SN74ALS74A is characterized
for operation from 0°C to 70°C.
Datasheet Available:Texas Instruments SN74ALS74A
SOIC 14 package. Manufactured by Texas Instruments.