The CY2308SC-5HT is a 3.3V Zero Delay Buffer designed to distribute high speed clocks in PC, workstation, datacom, telecom, and other high performance applications. The part has an on-chip PLL that locks to an input clock presented on the REF pin. The PLL feedback is driven into the FBK pin and obtained from one of the outputs. The input-to-output skew is less than 350 ps and output-to-output skew is less than 200 ps. The CY2308SC-5HT has two banks of four outputs each that is controlled by the Select inputs. If all output clocks are not required, Bank B is three-stated. The input clock is directly applied to the output for chip and system testing purposes by the select inputs.
The CY2308SC-5HT PLL enters a power down state when there are no rising edges on the REF input. In this mode, all outputs are three-stated and the PLL is turned off resulting in less than 50 ľA of current draw. Multiple CY2308SC-5HT devices accept the same input clock and distribute it in a system. In this case, the skew between the outputs of two devices is less than 700 ps. The CY2308SC-5HT is a high drive version with REF/2 on both banks.
Zero input-output propagation delay, adjustable by capacitive load on FBK input
Multiple low skew outputs
Two banks of four outputs, three-stateable by two select inputs
10 MHz to 133 MHz operating range
75 ps typical cycle-to-cycle jitter (15 pF, 66 MHz)
Datasheet Available:Cypress Semi CY2308SC-5HT
SOIC 16 package. Manufactured by Cypress Semiconductor.