The ispLSI 2064 125LJ is a high density programmable logic device. The device contains 64 registers, 64 universal I/O pins, four dedicated input pins, three dedicated clock input pins, two dedicated global OE input pins and a global routing pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2064 features 5V in-system programmability and in-system diagnostic capabilities. The ispLSI 2064 offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems.
The basic unit of logic on the ispLSI 2064 device is the generic logic block (GLB). The GLBs are labeled A0, A1 ... B7. There are a total of 16 GLBs in the ispLSI 2064 device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device.
125Mhz maximum operating frequency.
Datasheet Available:Lattice ISPLSI2064
PLCC 84 package. Manufactured by Lattice Semiconductor Corporation.