These positive-edge triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input, and features complementary
outputs from each flip-flop. Information at the D inputs meeting the setup and hold time requirements is transferred to the Q outputs on the positive going
edge of the clock pulse. Clock triggering occurs at a
particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output.
Contains four flip-flops with double-rail outputs
Buffered clock and direct clear inputs
Individual data input to each flip-flop
Typical clock frequency 40 MHz
Typical power dissipation per flip-flop 38 mW
Datasheet Available:National DM74175N
16 pin DIP. Manufactured by National.