The 74F841N bus interface latch series is designed to provide extra data width for wider address/data paths of buses carrying parity. The 74F841N series is functionally pin compatible to the AMD AM29841ľAM29846 series. The 74F841N consists of ten D-type latches with 3-State outputs. The flip-flops appear transparent to the data when Latch Enable (LE) is High. This allows asynchronous operation, as the output transition follows the data in transition. On the LE High-to-Low transition, the data that meets the setup and hold time is latched. Data appears on the bus when the Output Enable (OE) is Low. When OE is High the output is in the High-impedance state.
High speed parallel latches
Extra data width for wide address/data paths or buses carrying parity
High impedance NPN base input structure minimizes bus loading
Buffered control inputs to reduce AC effects
Ideal where high speed, light loading, or increased fan-in are required as with MOS microprocessors
Positive and negative over-shoots are clamped to ground
3-State outputs glitch free during power-up and power-down
48mA sink current
24 pin DIP. Manufactured by Signetics.