These octal bus transceivers are designed for asynchronous two-way communication between data buses. The control function implementation minimizes external timing requirements. The device allows data transmission from the A bus to the B bus or from the B bus to the A bus depending upon the logic level at the direction control (DIR) input. The enable input (G) can be used to disable the device so that the buses are
Bi-Directional bus transceiver in a high-density package
TRI-STATE outputs drive bus lines directly
PNP inputs reduce DC loading on bus lines
Hysteresis at bus inputs improve noise margins
Typical propagation delay times, port-to-port 8 ns
Typical enable/disable times 17 ns
SOIC 20 package. Actual brand may vary from picture.