The 74HC648s are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). The 74HC648 consist of bus transceiver circuits with 3-state inverting outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the internal registers. Data on the “A” or “B” bus will be clocked into the registers as the appropriate clock (CPAB and CPBA) goes to a HIGH logic level. Output enable (OE) and direction (DIR) inputs are provided to control the transceiver function. In the transceiver mode, data present at the high-impedance port may be stored in
either the “A” or “B” register, or in both. The select source inputs (SAB and SBA) can multiplex stored and real-time (transparent mode) data. The direction (DIR) input determines which bus will receive data when OE is active (LOW). In the isolation mode (OE = HIGH), “A” data may be stored in the “B” register and/or “B” data may be stored in the “A” register. When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, A or B, may be driven at a time. The 74HC648 has inverting data paths.
Independent register for A and B buses
Multiplexed real-time and stored data
Output capability: bus driver
ICC category: MSI
24 pin DIP (WIDE type). Actual brand may vary from picture.