The E28F320J5-120 contains high-density memories organized as 4 Mbytes or 2 Mwords (32-Mbit). These devices can be accessed as 8- or 16-bit words. This 32-Mbits device contains thirty-two 128-Kbyte erase blocks. Blocks are selectively and individually lockable and unlockable in-system.
A Common Flash Interface (CFI) permits software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent, and forward- and backward compatible software support for a specified flash device familiy. Flash vendors can standardize their existing interfaces for long-term compatibility. Scaleable Command Set (SCS) allows a single, simple software driver in all host systems to work with all SCS-compliant flash memory devices, independent of system-level packaging (e.g., memory card, SIMM, or direct-to-board placement). Additionally, SCS provides the highest system/device data transfer rates and minimizes device and system-level implementation costs. A Command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase, program, and lock-bit configuration operations.
A block erase operation erases one of the device’s 128-Kbyte blocks typically within one second— independent of other blocks. Each block can be independently erased 10,000 times. Block erasesuspend mode allows system software to suspend block erase to read or program data from any other block. This device incorporates a Write Buffer of 32 bytes (16 words) to allow optimum programming performance. By using the Write Buffer, data is programmed in buffer increments. This feature can improve system program performance by up to 20 times over non Write Buffer writes.
Individual block locking uses a combination of bits, block lock-bits and a master lock-bit, to lock and unlock blocks. Block lock-bits gate block erase and program operations while the master lock-bit gates block lock-bit modification. Three lock-bit configuration operations set and clear lock-bits (Set Block Lock-Bit, Set Master Lock-Bit, and Clear Block Lock-Bits commands).
The status register indicates when the WSM’s block erase, program, or lock-bit configuration operation is finished. The STS (STATUS) output gives an additional indicator of WSM activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). Status indication using STS minimizes both CPU overhead and system power consumption. When configured in level mode (default mode), it acts as a RY/BY# pin. When low, STS indicates that the WSM is performing a block erase, program, or lock-bit configuration. STS-high indicates that the WSM is ready for a new command, block erase is suspended (and programming is inactive), or the device is in reset/power-down mode. Additionally, the configuration command allows the STS pin to be configured to pulse on completion of programming and/or block erases.
Three CE pins are used to enable and disable the device. A unique CE logic design reduces decoder logic typically required for multi-chip designs. External logic is not required when designing a single chip, a dual chip, or a 4-chip miniature card or SIMM module.
The BYTE# pin allows either x8 or x16 read/writes to the device. BYTE# at logic low selects 8-bit mode; address A0 selects between the low byte and high byte. BYTE# at logic high enables 16-bit operation; address A1 becomes the lowest order address and address A0 is not used. When the device is disabled and the RP# pin is at VCC, the standby mode is enabled. When the RP# pin is at GND, a further power-down mode is enabled which minimizes power consumption and provides write protection during reset. A reset time (tPHQV) is required from RP# switching high until outputs are valid. Likewise, the device has a wake time (tPHWL) from RP#-high until writes to the CUI are recognized. With RP# at GND, the WSM is reset and the status register is cleared.
32 128-Kbyte Erase Blocks
5 V VCC Operation
Configurable x8 or x16 I/O
120 ns Read Access Time
32-Byte Write Buffer
320,000 Total Erase Cycles
TSOP 56 package. Manufactured by Intel.