The PALCE16V8-7JC is a CMOS Flash Electrical Erasable second-generation programmable array logic device. It is implemented with the familiar sum-of-product (AND-OR) logic structure and the programmable macrocell. This device provides up to 16 inputs and 8 outputs. The PALCE16V8-7JC can be electrically erased and reprogrammed. The PALCE16V8-7JC features 8 product terms per output and 32 input terms into the AND array. The first product term in a macrocell can be used either as an internal output enable control or as a data product term. There are a total of 18 architecture bits in the PALCE16V8-7JC macrocell; two are global bits that apply to all macrocells and 16 that apply locally, two bits per macrocell. The architecture bits determine whether the macrocell functions as a register or combinatorial with inverting or noninverting output. The output enable control can come from an external pin or internally from a product term. The output can also be permanently enabled, functioning as a dedicated output or permanently disabled, functioning as a dedicated input. Feedback paths are selectable from either the input/output pin associated with the macrocell, the input/output pin associated with an adjacent pin, or from the macrocell register itself.
All registers in the PALCE16V8-7JC power-up to a logic LOW for predictable system initialization. For each register, the associated output pin will be HIGH due to active-LOW outputs. An electronic signature word is provided in the PALCE16V8-7JC that consists of 64 bits of programmable memory that can contain user-defined data. A security bit is provided that defeats the readback of the internal programmed pattern when the bit is programmed. The PALCE16V8-7JC provides low-power operation through the use of CMOS technology, and increased testability with Flash reprogrammability. Product Term Disable (PTD) fuses are included for each product term. The PTD fuses allow each product term to be individually disabled.
Active pull-up on data input pins
Standard version, low power: 115 mA max. commercial (7 ns)
CMOS Flash technology for electrical erasability and reprogrammability
-Output polarity control
-Individually selectable for registered or combinatorial operation
Up to 16 input terms and eight outputs
7.5 ns com’l version
5 ns tCO
5 ns tS
7.5 ns tPD
125-MHz state machine
-Proven Flash technology
-100% programming and functional testing
PLCC 20 package. Manufactured by Cypress Semiconductor.