The GAL16V8D-15LJ, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.
High Performance E2CMOS® Technology
50% to 75% Reduction in Power from Bipolar
Active Pull-Ups on all Pins
Eight Output Logic Macrocells
Preload and Power-On Reset of all Registers
State Machine Control
High Speed Graphics Processing
Standard Logic Speed Upgrade
Datasheet Available:Lattice GAL16V8D-15LJ
20-Lead PLCC package. Manufactured by Lattice.