These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset and clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high. The SN74LS114AJ is characterized for operation from 0°C to 70°C.
Fully buffered to offer maximum isolation from external disturbance
Datasheet Available: Texas Instruments SN74LS114AJ
14 pin DIP. Manufactured by Texas Instruments.